Modern integrated circuit devices continue to shrink in size as they accelerate in speed. More and more functionality is demanded of less and less device “real estate” or available circuit space, whether on the printed circuit board of an electronic appliance or on the semiconductor die in which integrated circuits are formed.
Existing integrated circuits are essentially two-dimensional in that they are formed on the surface of flat semiconductor wafers. Until the advent of the stacked-die assembly, notwithstanding the development of limited multi-layer circuitry, the only ways to increase the complexity of a circuit were to increase the area of semiconductor used or to shrink feature size.
Stacked die technology has taken semiconductor fabrication into the third dimension, allowing a potentially large number of stacked dice to put very complex devices into small appliance footprints. The additional advantage of thin wafer technology combines to put very complex circuitry in the same footprint as a single die.
Stacking dice, though, brings on new challenges. Stacking requires that a daughter die be attached to a mother die, typically by an array of solder bumps, and requires that the mother die have contactable points on both surfaces. This means that both surfaces of the mother die must be addressed during processing.
Dual-surface processing requires some means of holding the die in a processing fixture. The holding and manipulation is hampered by the fragility of circuitry formed in the surface of the die and, if formed, the presence of solder bumps. These handling difficulties add expense, complexity and time to the fabrication process. Furthermore, because dice are typically stacked on solder bump arrays, the issues that must be dealt with include alleviating mechanical stresses as well as assuring electrical connectivity during manufacturing.